Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback

Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, Zhe Jiang·April 22, 2025

Summary

A method improves training of Verilog generation LLMs by integrating verification insights. It uses an automatic testbench generation pipeline with feedback from the Verilog compiler simulator, enhancing functional correctness. This surpasses state-of-the-art baselines in generating functionally correct Verilog code, addressing the scarcity of functional verification data.

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